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the psb 2120 is a pulse width modulator (pwm) circuit designed for fixed-frequency switching regulators especially for telephony and isdn-environments. the psb 2120 is fully compatible with the ccitt-power recommendations on the s-interface. coupled with a few external components it can provide a stable 5 v dc-supply for subscriber terminals (tes) or network terminators (nts). it can also be programmed for higher output voltages, e.g. to supply the s-lines with 40 v. in telephony and isdn-systems a high conversion yield is crucial to maintain functionality in all supply conditions via s- or u-interfaces. the psb 2120 design and technology realizes high conversion efficiency and low power dissipation. it should be recognized that the psb 2120 can also be used in numerous dc/dc-conversion systems other than isdn-power supplies. type version ordering code package psb 2120-p v b5 q67100-h8645 p-dip-22 psb 2120-t v b5 q67100-h6278 p-dso-24-1 (smd) isdn remote power controller (irpc) cmos ic psb 2120 p-dso-24-1 p-dip-22 features l switched mode dc/dc-converter l switched mode dc/dc-converter l ccitt (i.430) isdn compatible l integrated 200 v power fet (only psb 2120-p in p-dip-22) l low power dissipation l supply voltage range 10 v to 60 v l input undervoltage detection l programmable overcurrent protection l soft start l control circuit to achieve minimum start-up current l power housekeeping input l oscillator synchronization input/output l polarity reversal detection l high voltage cmos-technology 60 v semiconductor group 3 12.92
semiconductor group 2 p-dso-24 p-dip-22 pin configurations (top view) psb 2120
semiconductor group 3 psb 2120 pin definitions and functions pin no. p-dso pin no. p-dip symbol input (i) output (o) definition function 1 1 sync i/o synchronization input for synchronization of the oscillator to an external frequency, or output to synchronize multiple devices. 2 2 rc i rc-oscillator the external timing components of the ramp generator are attached to this pin. 3 3 comp o compensation error amplifier output and p ulse w idth m odulator (pwm) input for loop stabilization network. 44 v p i positive voltage sense non-inverting input of the error amplifier. 55 v n i negative voltage sense inverting input of the error amplifier. 66 c ss i soft start capacitor the capacitor at this pin determines the soft-start characteristic. 77 eme o emergency a low input voltage at pol will activate the output eme. 8 8 pol i polarity detection pol is the input to a non inverting schmitt-trigger. 11 9 ga o gate output of the fet-driver. n.c. 10 dr o drain drain connection of the power fet. n.c. 11 so o source source connection of the power fet. 14 12 c in i input capacitor c in has to be connected to the input buffer-capacitor and a current limiting charging-resistor.
semiconductor group 4 pin definitions and functions (contd) pin no. p-dso pin no. p-dip symbol input (i) output (o) definition function 15 13 ena i enable a high input voltage at this pin will stop the irpc-function. 16 14 co o comparator output connections of the universal usable comparator. 17 15 cn i comparator neg. input 18 16 cp i comparator pos. input 19 17 gnd i ground all analog and digital signals are referred to this pin. 20 18 v ext i/o external supply output of the internal cmos-supply. via v ext the internal cmos-circuits can be supplied from an external dc-supply in order to reduce chip power dissipation. 21 19 i n i negative current sense when the voltage difference between these two pins exceeds 100 mv, the digital current limiting becomes active. 22 20 i p i positive current sense 23 21 v ref o reference voltage output of the 4.0 v reference voltage. 24 22 v s i supply voltage v bat is the positive input voltage. psb 2120
semiconductor group 5 psb 2120 figure 1 irpc functional diagram
semiconductor group 6 functional description the reference provides a 4.0 v voltage for the regulation loop. a high gain error amplifier compares the reference voltage with the switch mode supply output voltage. the output of the error amplifier is compared with a periodic linear ramp, which is generated by the sawtooth-oscillator circuit. the comparator output is a fixed-frequency, variable pulse width logic signal, which passes through logic circuits to the high voltage power-switching-fet. a digital current limiting device suppresses the pwm logic signal when the voltage difference at the current limit sense input reaches 100 mv. in this case the control logic inhibits double pulses during one oscillator period. start-up procedure before the switched-mode dc/dc-converter starts, a sequence of several conditions has to be passed in order to avoid any system malfunction. the primary undervoltage detection inhibits the converter function. this insures that all control functions have stabilized in the proper state when the turn on voltage (ca. 10 v) is reached, and it prevents start-up glitches. in case of connecting the te to powered lines or if a line is powered up, the charge current of the primary buffer capacitor is limited by an external resistor ( figure 2 ). this resistor is short-circuited by the psb 2120 when the voltage drop across it falls below approximately 2.0 v. the residual resistance of this short-circuit is about 3 w . in case of a primary undervoltage detection the short-circuit will be always deactivated. so, the dc/dc-converter does not start until the charging of the primary buffer capacitor is completed, and the maximum line input voltage is reached. if this feature is not desired, c in has to be connected to gnd. in this case the primary current measuring circuit turns off, to reduce chip-power dissipation from 9 mw to 6 mw. in order to avoid high current peaks during the charging of the secondary capacitors or line capacitors in case of supplying an s-interface, a soft start circuit is implemented in the psb 2120. this circuit requires an external capacitor, connected between c ss and gnd. in addition, the enable input ( ena) allows an external switch-on/switch-off control. if the dc/dc- converter is disabled via ena, the soft-start-capacitor at pin c ss is discharged. this input can also be used for several other functions, e.g. secondary overvoltage protection. psb 2120
semiconductor group 7 psb 2120 figure 2 dc/dc-conversion the psb 2120 contains a sipmos-transistor for power handling. non-isolated and isolated smps- configurations are possible. logic and analog circuits are implemented in cmos in order to achieve low power dissipation. the error amplifier compares the sensed voltage with a reference attached to v p and thus controls the pulse width modulator (pwm). the conversion frequency is generated by a sawtooth oscillator which can be controlled by external rc-components ( figure 4 ) or by an external synchronization signal. the psb 2120 is synchronized by the rising edge of the sync signal, whose frequency must be 10 % higher than the free run frequency, determined by the rc-components. the sync-pin can also be used as a trigger-output. as long as the capacitor of the sawtooth oscillator is discharged, sync is high. the output of the pwm is processed by the control logic and fed to the sipmos-transistor. the control logic suppresses higher oscillations of the regulation loop caused e.g. in case of current limit detection.
semiconductor group 8 polarity detection emergency conditions are signaled to the te by the reversed polarity of the line feeding voltage. when polarity reversal is detected via pin pol of the psb 2120, emergency conditions are signaled to the microprocessor via pin eme, which should shut down all activity except simple telephony functions to minimize power dissipation. the polarity detection circuit can also be used for other detection or protection-functions, e.g. programmable primary undervoltage detection. power housekeeping an integrated 6 v linear voltage regulator supplies the internal circuits during the start-up phase. power dissipation of this regulator can be reduced, if an auxiliary winding of the transformer or an external supply is used for that purpose by connecting it to v ext . if the input voltage at v ext reaches 6.2 v the internal linear voltage regulator turns off and the internal circuits are fed from this external voltage. in this case the input current at v ext is approx. 0.5 ma. note : an internal 7.5 v zener-diode protects the v ext input against overvoltages. the maximum zener-current is 2 ma! if the external supply isnt stabilized, the input current must be limited (e.g. by a resistor)! interface to microprocessor the psb 2120 offers two ttl-compatible signals: eme and co. the eme (emergency-output) becomes active, if polarity reversal is detected. co is the output of a universal usable comparator; e.g.: to generate a microprocessor-reset signal. psb 2120
semiconductor group 9 psb 2120 psb 2120 applications in isdn-environments figure 3 shows an example out of the wide application field of the psb 2120. in the network termination one psb 2120 supplies the internal ics directly from the uCinterface. a second irpc, also powered from the u-line, supplies the sCinterface if the main supply of the nt is out of order. a third irpc is used in the main supply to regulate the s-line feeding voltage. in the subscriber terminal the psb 2120 is used for feeding the internal circuits. the psb 2120 accommodates both galvanically isolated and non-isolated configuration. considering the diversity of dc/dc-converter applications, this part of the specification only shows how to use the special isdn-features of the psb 2120. the switching frequency of the smps is programmable by two external components. figure 4 shows the switching frequency as a function of r t and c t . the minimum configuration so as to be able to use the psb 2120 in isdn-applications is by using a flyback converter ( figure 5 ). the time constant of the soft start circuit is programmed by a capacitor at pin c ss . figure 6 shows the primary start-up current limitation by connecting pin c in . to reduce chip-power- dissipation, an auxiliary winding of the transformer is used to switch off the internal linear cmos- supply (pin v ext ). polarity reversal is detected by pin pol. figure 7 shows the realization of a microprocessor-reset-signal with the universal usable comparator of the irpc. figure 8 shows the psb 2120 in flyback configuration with transformer isolation. figure 9 shows the psb 2120 in flyback configuration with opto isolation, which is useful for a high reliability galvanically isolated application.
semiconductor group 10 figure 3 irpc in isdn-concept psb 2120
semiconductor group 11 psb 2120 figure 4 switching frequency as a function of r t and c t switching frequency
semiconductor group 12 figure 5 psb 2120 minimum configuration psb 2120
semiconductor group 13 psb 2120 figure 6 advanced irpc-application with power housekeeping and polarity reversal detection
semiconductor group 14 figure 7 generation of a m p-reset signal with the psb 2120 according to the application in figure 5 and an output power of 500 mw, t 1 will be 400 ms and t 2 50 ms. psb 2120
semiconductor group 15 psb 2120 figure 8 psb 2120 in flyback configuration with transformer isolation
semiconductor group 16 figure 9 psb 2120 in flyback configuration with opto isolation psb 2120
semiconductor group 17 psb 2120 absolute maximum ratings (all pin references made for p-dip-22) mos-handling: the integrated sipmos-transistor (pin 9, 10 and 11) has to be protected against electrostatic charges. the input gate-source (pin 9 and pin 11) must be protected against 10 v. dc characteristics t a = 0 to 70 ?c, v s = 11 to 60 v parameter symbol limit values unit supply voltage dr (pin 10) referred to s0 (pin 11) v s 200 v continuous drain current (pin 10) i dr 350 ma supply voltage v bat (pin 22) referred to gnd v bat 60 v analog/digital input voltage referred to gnd (pins 2, 3, 4, 5, 7, 8, 13, 15, 16, 19, 20) v i a/d 6v reference output current (pin 21) i o ref C 5 ma v ext input z-current i i z 2ma v ext output current i o C 5 ma sync-output current (pin 1) i o sync C 5 ma driver output current (pin 9) i o dr C 5 ma ambient temperature under bias t a C 25 to 85 ?c storage temperature t stg C 40 to 125 ?c thermal resistance junction C ambient t j 50 k/w parameter symbol limit values unit test condition min. typ. max. reference v ref t a = 25 ?c output voltage v ref o 3.92 4.0 4.08 v i l = 0 ma, v s = 40 v line regulation v ref line 60 mv v s = 20 to 60 v, i l = 0 ma, load regulation v ref load 20 40 mv i l = 0.1 to 0.3 ma, v s = 40 v temperature stability v ref ts 25 mv load current i ref load 0.5 ma
semiconductor group 18 dc characteristics (contd) parameter symbol limit values unit test condition min. typ. max. oscillator sync (pin1) , rc (pin 2) f osc = 20 khz, r t 39 k w 1 %, c t = 1 nf 1 %, t a = 25 ?c initial accuracy 10 % voltage stability of f osc 13% temperature stability of f osc 5% max. frequency f max 180 250 khz r t = 27 k w c t = 39 pf h-sawtooth voltage v h 3.0 3.2 3.4 v l-sawtooth voltage v l 1.6 1.8 2.0 v h-sync output level v oh 2.4 3.5 5.25 v i l = 0.5 ma v s ext 6.3 v l-sync output level v ol 0.2 0.8 v i l = 20 m a error amplifier comp (pin 3), v p (pin 4), v n (pin 5) input offset voltage v io 310mv v cm = 3.0 v input current i i 025na common mode range v c 1.8 4.0 v v offset = 15 mv dc open loop gain g vo 60 70 db common mode rejection k cmr 60 70 db unit gain bandwidth f 0.5 1 mhz c l (pin) 10 pf supply voltage rejection 60 70 db h-output voltage v oh 4 5.5 v i l = 100 m a l-output voltage v ol 0.02 v i l = 10 m a current limit comparator i p (pin 20), i n (pin 19) t a = 25 ?c sense voltage v sense 85 100 115 mv v s = 40 v input current i i 0 100 na input voltage range v i 01v response time to signal at ga (pin 9) t res 12 m s i n = 0 v i p = 0 ? 200 mv psb 2120
semiconductor group 19 psb 2120 dc characteristics (contd) parameter symbol limit values unit test condition min. typ. max. pulse width modulator duty cycle t d 050% undervoltage detection start-up threshold v uv st 8.1 10 11 v threshold hysteresis v uv hy 0.3 v soft start c ss (pin 6) charging current i c 248 m a output driver ga (pin 9) t a = 25 ?c, c l = c gs C power fet h-output voltage v oh 4.5 v i source = 5 ma h-output voltage v oh v ext v i source = 0 ma l-output voltage v ol 0.3 0.4 v i sink = 5 ma rise time t r 130 200 ns v ext = 6.3 v fall time t f 70 200 ns v ext = 6.3 v output current i o 5ma external supply v ext (pin 18) output voltage v o 5.8 v output current i o 2ma input voltage v i 6.0 7.5 v z-current i z 2ma enable input ena (pin 13) h-input voltage v ih 2.0 5.25 v l-input voltage v il 0.8 v response time to signal at ga (pin 9) t res 0.5 1 m s t a = 25 ?c h-input current i ih 0.2 2.5 20 m a
semiconductor group 20 dc characteristics (contd) parameter symbol limit values unit test condition min. typ. max. comparator cn (pin 15), cp (pin 16), t a = 25 ?c input offset voltage v io 310mv v cm = 3 v input bias current i i 025na input voltage range v i 1.8 4.5 v response time to signal at co (pin 14) t res 0.2 1 m s short circuit g i (pin 12), t a = 25 ?c sense voltage v sense 123v (v s C v cin ) r ds (on) 34 w polarity detection pol (pin 8), eme (pin 7) h-input voltage v ih 2.0 5.25 v l-input voltage v il 0.8 v h-input current i ih 0.1 1 10 m a response time to signal at eme (pin 7) t res 0.2 1 m s digital outputs eme (pin 7), co (pin 14) i out = 0.5 ma h-output voltage v oh 2.4 3.5 5.25 v v ext 6.3 v l-input voltage v il 0.2 0.4 v power fet ga (pin 9), dr (pin 10), so (pin 11) r ds (on) 46 w i d = 300 ma t on t d (on) 55 150 ns t off t d (off) 110 200 ns leakage current i leak 200 na v ds = 110 v power consumption p tot 910ma v s = 40 v f osc = 20 khz v ext = 6.3 C 6.7 v c gs 200 pf psb 2120

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